A typical network switch (or router) has a hardware-based fast path for forwarding packets, and a software/CPU-based slower path for learning packet addresses and connections. Specifically, a network switch (or router) typically includes dedicated hardware for forwarding network packets at high speed by using forwarding table lookups (e.g., hashing, content addressable memories or CAMS, etc.), and one or more central processing unit (CPU) subsystems that are used to program the forwarding tables. The CPU is also responsible for maintaining network operation by using specific network protocols (e.g., handling route updates, address resolution protocol or ARP queries/replies, Internet Control Message Protocol or ICMP messages, spanning tree related packets, etc.) as well as user interface functionality. Networking protocol packets are necessary in order to keep the network operational and are typically sent for processing to the CPU.
Packets that are sent to a CPU (i.e., packets that are “copied”) are typically prioritized into one of a number of CPU queues (typically from 2 to 8 queues). The memory space of the CPU will typically contain these queues that will be serviced in priority order, i.e., packet traffic placed in the highest priority queue will be processed first before processing packet traffic placed in the lower priority queues. Packets in the lower priority queues may even be discarded should the packet rate to the CPU exceed the packet rate which the CPU can actually process. Thus it is important to correctly prioritize packets into the correct CPU queue. Prior solutions to this problem are typically static and are based on simplistic criteria, and as a result, these prior solutions are suboptimal.
Therefore, the current technology is limited in its capabilities and suffers from at least the above constraints and deficiencies.